A Parallel Microprocessor Architecture for Electronic Countermeasures Processing.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OHIO SCHOOL OF ENGINEERING
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The large number and wide variety of radio frequency emitters encountered in electronic warfare provide an enormous quantity of data for an electronic countermeasures system to process. Historically, all data has had to pass through a central processor for threat identification. Speed is the primary requirement for this ECM processor. In this thesis the concept of parallelism was investigated as a method to increase the throughput of existing processors. Microprocessors were employed as the individual processing elements in a single data stream - multiple instruction stream architecture. Data steering or vectoring was accomplished via the use of programmed logic arrays stored in random access memories. To test the feasibility of a parallel microprocessor architecture for ECM processing its basic building blocks were simulated. The necessary control logic, which is implemented in software in a master control processor, includes the capability to adapt the architecture to deal with the unpredictable nature of ECM data. A fictitious scenario was developed to stimulate the data steering logic and test the master processors capability to handle system overloads. Also, the actual ability of the system to process data was simulated through the use of fictitious radar parameters. Author
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