Electrical Overstress Test Program and Integrated Circuit Failure Mode Evaluation.
Final rept. May-Oct 77,
BDM CORP ALBUQUERQUE N MEX
Pagination or Media Count:
This final report describes the SOS diode test structures which will be used for empirical investigation of electrical overstress failure. The test structures, in which important physical parameters are varied, are described in detail and a test plan is presented for the overstress testing that will generate failure data for a sensitivity analysis of pulse power failure level as a function of junction area, epitaxial thickness, junction radius of curvature, doping level and metallization and diffusion spikes. An electrical overstress failure mode and distribution study in integrated circuits is presented. Data on over 1200 devices which were tested on previous programs was analysed to determine failure modes on DTL, RTL, TTL, ECL, MOS and linear integrated circuits. The failure distributions on over 3,000 devices from several different test programs were reviewed to identify mavericks. These mavericks were investigated for distinctive failure modes or unusual preirradiation electrical characteristics. Author
- Electrical and Electronic Equipment