Accession Number:

ADA056190

Title:

Complexity Reduction in Galois Logic Design.

Descriptive Note:

Final rept. Feb-Dec 77,

Corporate Author:

SPERRY UNIVAC ST PAUL MINN DEFENSE SYSTEMS DIV

Personal Author(s):

Report Date:

1977-12-01

Pagination or Media Count:

43.0

Abstract:

Two methods of reducing the complexity of the hardware used in Galois logic design are presented reduced trees of Galois linear modules, and subfield multipliers. The first method lowers the number of modules in a full tree of Galois linear modules and the second method enables multiplication in a Galois field to be done with subfield multipliers. Author

Subject Categories:

  • Theoretical Mathematics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE