Complexity Reduction in Galois Logic Design.
Final rept. Feb-Dec 77,
SPERRY UNIVAC ST PAUL MINN DEFENSE SYSTEMS DIV
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Two methods of reducing the complexity of the hardware used in Galois logic design are presented reduced trees of Galois linear modules, and subfield multipliers. The first method lowers the number of modules in a full tree of Galois linear modules and the second method enables multiplication in a Galois field to be done with subfield multipliers. Author
- Theoretical Mathematics