Linear Time-Delay Generator Using ECL Technology.
TENNESSEE UNIV KNOXVILLE
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The purpose of this research project was to develop a wide-range, linear, time-delay circuit having an output pulse that is compatible with ECL logic levels. The circuit requires an input pulse width of 4 nsec, has a propagation delay of 8 nsec, and has rise and fall times of 2 nsec on the output pulse. The linearity error between the delay generated and the delay dial setting is less than 1. The output pulse jitter is less than 0.2. The circuit is retriggerable in 3 nsec. The wide-range, linear, time-delay circuit was developed using ECL technology. The voltage comparison functions were performed by four AM685s which are high-speed ECL voltage comparators. The various logic functions were performed with three MECL integrated circuit chips. One MC10104 IC performed AND and NAND logic functions and two MC10105 ICs performed OR and NOR logic functions. The circuit used a minimum number of discrete components. Author
- Electrical and Electronic Equipment
- Test Facilities, Equipment and Methods