NOPAL Processor: Intra-Test Sequencing.
Final rept. 30 Jun 75-31 Aug 77,
MOORE SCHOOL OF ELECTRICAL ENGINEERING PHILADELPHIA PA DEPT OF COMPUTER AND INFORMATION SCIENCES
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This report describes the algorithms, methods, and programs that represent the intra test sequencing phase of the NOPAL processor. The overall objective of the NOPAL system is to generate a program for computer controlled automatic test equipment for testing an electronic unit under test. The input to the system is a nonprocedural description of the desired test expressed in the NOPAL language. The present report describes how such a specification can be analyzed and how a flowchart can be generated for performing the test. A subsequent phase of NOPAL generates a program based on the flowchart. The report can be read independently of the NOPAL processor. Readers interested only in the automatic sequencing of operations in a program can omit Chapters 1 and 2, which describe the NOPAL language and processor. Readers interested in greater detail on the NOPAL processor can obtain further information in the references listed in the bibliography. Author
- Computer Programming and Software
- Test Facilities, Equipment and Methods