Accession Number:

ADA053269

Title:

Bus Interface Unit Design for the Distributed Processor/Memory System.

Descriptive Note:

Master's thesis,

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OHIO SCHOOL OF ENGINEERING

Personal Author(s):

Report Date:

1977-12-01

Pagination or Media Count:

231.0

Abstract:

This report describes the design of the Bus Interface Unit for the Distributed ProcessorMemory DPM System. The DPM System, which is being developed by the Air Force Avionics Laboratory, is a concept to integrate avionics on board an aircraft by utilizing a number of programmable processormemory elements PEs in a distributed decentralized network. All the PEs in the system are interconnected by a pair of redundant global buses and PEs in an affinity group are additionally interconnected by a local bus. This effort involves the design of the Bus Interface Unit BIU of the PE. The BIU interfaces the parallel-data PE processor with the two redundant serial global buses and the serial local bus. The BIU has been designed as an interrupt driven microprogrammed processor. The design uses a bipolar bit-slice microprocessor, specifically the Am2900 Bipolar Microprocessor Family, for emulating the BIU functions. This report starts with a brief description of the DPM System, followed by a detailed description of the BIU functions. Then the hard-ware, the microword format, and the microroutines are described. A discussion on the design effort is presented at the end, and recommendations are made for system improvement. Author

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE