Digital Smoothing Buffer.
Rept. for Jul 75-Sep 77,
ROME AIR DEVELOPMENT CENTER GRIFFISS AFB N Y
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Asynchronous time division multiplexers ATDMs typically produce large phase excursions as a result of bit stuffing operations. Analog phase locked loops PLL are normally employed to smooth these excursions to levels which can be accepted by various sink equipments. For ATDMs which cover a broad range of rates, such as the ANGSC-24, it is difficult to provide a high level of smoothing across the entire range due to noise and frequency limitations. This project investigated a digital PLL as a potential technique for circumventing the analog limitations. A digitally implemented PLL has the potential of providing extended smoothing across a broad range of rates as smoothing becomes a function of the number of stages of circuitry implemented. The constraints on the project were to determine if a digital second order PLL could be implemented on an ANGSC-24 size circuit card which would be capable of providing a slew rate of less than 2 pi radians over a 20,000 bit interval. It was determined that this slew rate goal could be reached over a wide range of data rates but high frequency phase jitter and size limitation have made it undesirable for ANGSC-24 use. Author
- Non-Radio Communications