Accession Number:

ADA043361

Title:

An Algorithm for Minimizing Programmable Logic Array Realizations.

Descriptive Note:

Technical rept.,

Corporate Author:

ILLINOIS UNIV AT URBANA-CHAMPAIGN COORDINATED SCIENCE LAB

Personal Author(s):

Report Date:

1977-04-01

Pagination or Media Count:

99.0

Abstract:

Due to the increasing use PLAs Programmable Logic Arrays in logic design, and efficient algorithm which performs multiple-output AND-OR logic minimization is desired. Quine-McCluskey QM logic minimization has been known for some time. A new AND-OR minimization algorithm for logic problems with up to 16 inputs and 8 outputs standard limitations of PLAs available at present is needed. The algorithm should be particularly effective for problems which require no more than 40 to 50 product terms in an optimum realization. In this report, such an algorithm is formulated which strives to achieve an AND-OR realization with the smallest number of AND gates.

Subject Categories:

  • Computer Programming and Software
  • Computer Hardware
  • Computer Systems

Distribution Statement:

APPROVED FOR PUBLIC RELEASE