Accession Number:

ADA036217

Title:

The Architecture of a Database Computer. Part III. The Design of the Mass Memory and Its Related Components.

Descriptive Note:

Technical rept.,

Corporate Author:

OHIO STATE UNIV COLUMBUS COMPUTER AND INFORMATION SCIENCE RESEARCH CENTER

Personal Author(s):

Report Date:

1976-12-01

Pagination or Media Count:

145.0

Abstract:

This is the last of the three-part series which deals with the design of a back-end computer known as the database computer DBC. The concepts and capabilities of the DBC were presented in Part I. Schematically, the DBC architecture consists of two loops of memories and processors, namely, the structure loop and the data loop. The structure loop is composed of four components the structure transformation unit KXU, the structure memory SM, the structure memory information processor SMIP and the index translation unit IXU. The design philosophy, implementation details and hardware organizations of the structure loop components were documented in Part 2. In this report, the design of the data loop is presented. In addition, the database command and control processor DBCCP, which regulates the operations of both the structure and data loops and interfaces with the front-end computer systems, is also presented. The DBCCP processes all DBC commands received from the front-end computer systems, schedules the execution of the commands on the basis of the command type and priority, enforces security on a selective basis, clusters records to be stored in the DBC and routes the response set to the front-end computer systems.

Subject Categories:

  • Computer Programming and Software
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE