An Integrated Circuit Fault Model for Digital Systems.
ILLINOIS UNIV AT URBANA-CHAMPAIGN COORDINATED SCIENCE LAB
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A model for the faulty behavior of digital networks realized using integrated circuit devices is proposed. This model, the pin fault assumption, is based on a study of the most frequently encountered failure mechanisms for such networks, and the observation that previous fault assumptions model a large number of faults which occur with low frequency. The basis for the pin fault model, and an investigation of multiple fault detection using this model are presented. Fault detection for combinational modules is investigated, and it is shown that multiple pin fault detection test sets for such modules may be quite easily generated. The computation required to generate such test sets is independent of the circuit realization internal to the model, and each test generated requires about the same amount of computation. The computational complexity of test generation is greatly reduced compared to that for previously studied fault models. Pin fault detection experiments for sequential machines are studied, and methods for designing such experiments are developed. These design methods are compared to those under other fault assumptions, and a substantial reduction is observed in the length of such sequences and the computation required to produce them. Author
- Electrical and Electronic Equipment