A Virtual Memory System for the PDP-10 KA10 Processor.
Final technical rept. Jul 75-Mar 76,
CALIFORNIA UNIV LOS ANGELES DEPT OF COMPUTER SCIENCE
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This report describes the development of the Large Space Virtual Memory System for operation with a Digital Equipment Corporation PDP-10 Computer system. The virtual memory system modifies the KA10 instruction set and addressing mechanisms to provide a virtual memory address space of 2 to the 36th power 36-bit words. Each address consists of a 9 bit segment number and a 27 bit within segment address. The VM control programs are based on a new page replacement algorithm, the Page Fault Frequency PFF Replacement Algorithm, called the Shared PFF SPFF. Author
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