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Manufacturing Methods and Technology Project to Establish and Improve the Producibility of Silk Screening and Layering of Ceramic Dielectric Capacitors.
Quarterly progress rept. no. 3, 1 Jan-1 Apr 76,
USCC/CENTRALAB LOS ANGELES CALIF
Pagination or Media Count:
A summary manufacturing methods and technology engineering for silk screening and layering three dielectric capacitor types is presented. Chip capacitors to be manufactured using .0005 inch dielectric rated at 50 volts at a pro-dunction rate of 5000 units per day. Internal electrodes shall be of a basemetal or alloy that will provide for an objective of 80 cost reduction from the use of palladuim. End terminations shall be of the same material and must be capable of immersion for seconds at 500F in 6040 solder.
APPROVED FOR PUBLIC RELEASE