LSI Digital Frequency Synthesizer.
Final rept. 14 Mar 74-16 Jun 75,
NORTHROP RESEARCH AND TECHNOLOGY CENTER HAWTHORNE CALIF
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Results are presented on the development of an integrated injection logic I2L digital frequency synthesizer DFS. The prototype DFS was designed to operate at a 4.8 MHz clock rate outputting eight fixed frequencies from dc to 2.4 MHz. The processing, testing and evaluation of I2L logic test cells is reported. The minimum stage delay achieved for a test I2L inverter was 8.7 ns. The design rules applicable to standard cell large scale I2L are discussed. The prototype DFS design, layout and testing is presented. Approximately 640 basic I2L inverters were required to implement the prototype DFS. Average power dissipation at the 4.8 MHz clock rate is estimated to be 20 microW per inverter. The feasibility of future expansion of the DFS to provide 640 frequencies at 4.8 MHz and 128 frequencies at 12.5 MHz clock rate is discussed. Author
- Electrical and Electronic Equipment