Damage Profiles in Silicon and Their Impact on Device Reliability
Technical rept. no. 7, 1 Jul-31 Dec 1975
IBM CORP HOPEWELL JUNCTION NY EAST FISHKILL LABS
Pagination or Media Count:
Impact Sound Stressing of silicon wafers is used to measure the effectiveness of various polishing techniques used to prepare silicon surfaces free of damage. Modern chemical-mechanical polishing techniques such as silicon dioxide and cupric ion polishing are more successful in damage removal than chemical polishing techniques which use mixtures of nitric, hydrofluoric and acetic acids. All polishing techniques are more or less limited in regenerating minority carrier lifetime in mechanically damaged silicon surfaces through surface repolish. Transmission electron microscopy analysis of Hertzian fracture cones and abrasive damage introduced through ISS into 001 silicon surfaces is performed. The analysis is made before and after high temperature oxidation. Dislocation patterns are analyzed before and after oxidation annealing. It is shown that crack stresses in silicon are not relaxed at room temperature. Annealing of dislocation bands produces stacking faults in areas of high density dislocation clusters. The stacking faults are identified as annealing products of microsplits. Finally, it is shown that damage propagation does not occur through the wafer towards the non-stressed surface before or after annealing.
- Electrical and Electronic Equipment
- Solid State Physics