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Simulation and Design of a Digital Data Compressor.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OHIO SCHOOL OF ENGINEERING
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The memory required to store the output from analog to digital converters is a problem at the Air Force Weapons Laboratory because of the volume of information that needs to be saved. To reduce the memory requirements, a digital data compression technique was developed. The algorithm used, its simulation on a computer, and a hardware design based on it are discussed in this report. The algorithm is based on amplitude and slope differences from successive points from an analog to digital converter. The computer simulation showed that memory requirements could be reduced by as much as ninety percent using this algorithm on transient signals. The hardware design enables further testing and evaluation with actual signals from field tests.
APPROVED FOR PUBLIC RELEASE