Transient Surface Damage and Latchup in CMOS Devices.
Final rept. 13 May 74-12 May 75,
RESEARCH TRIANGLE INST RESEARCH TRIANGLE PARK N C
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The work consists of concurrent studies of transient surface damage and latchup phenomena in irradiated CMOS devices. Isothermal V sub th annealing data are presented for CMOS 4007 inverters from 0.0001 to 0.001 sec after exposure to ionizing radiation pulses. Commercial and research samples prepared on bulk silicon as well as silicon-on-sappire substrates are evaluated. High and low temperature annealing data are used to develop extended room temperature annealing characteristics over the 0.000001 and 10 to the 8th power sec post exposure interval. Electrical measurements and radiation tests have been conducted on selected commercial CMOS devices in an assessment of their susceptibility to radiation-induced latchup. A latchup problem has been identified in four of the thirteen circuit types tested. Test results along with some techniques for avoiding latchup are discussed.
- Electrical and Electronic Equipment
- Radioactivity, Radioactive Wastes and Fission Products