Accession Number:

ADA010625

Title:

Design and Evaluation of an Arithmetic Unit.

Descriptive Note:

Interim rept. Jan 72-Dec 73,

Corporate Author:

SYRACUSE UNIV N Y

Personal Author(s):

• Feng,Tse-yun
• Hsu,Chung-ping

Report Date:

1975-03-01

Pagination or Media Count:

136.0

Abstract:

Iterative array logic and several existing arrays for arithmetic operations are first reviewed. Then, for a large scale general purpose associative processor a modularized arithmetic unit is proposed and studied. The proposed arithmetic unit has the flexibility to perform arithmetic operations with any multiple of four bits being processed in parallel. While reducing the total number of words that can be processed simultaneously by a corresponding factor, the per-word execution time is decreased proportionally. This design will partially solve the problem of inefficient utilization of hardware facilities, especially arithmetic unit, for smaller applications. Algorithms are flow-charted and illustrated for full-length parallel and four-bit parallel arithmetic operations, which exemplify various parallel arithmetic operations. Finally, a comparison study is provided concerning full-length parallel and m-bit parallel operations for various m, which is a multiple of 4 and less than the operand length.

Descriptors:

• *PARALLEL PROCESSORS
• *ASSOCIATIVE PROCESSING
• *ARITHMETIC UNITS
• ALGORITHMS
• LOGIC DEVICES

Subject Categories:

• Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE