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Reliability Evaluation of C/MOS Technology in Complex Integrated Circuits.
Interim rept. 8 May 73-30 Sep 74,
RCA SOLID STATE DIV SOMERVILLE N J
Pagination or Media Count:
The objective of the study is to investigate reliability on small and medium scale CMOS integrated circuits. Four manufacturers gates and three manufacturers shift registers are included. The effects of burn-in and stress tests on the devices are being evaluated. One aspect of this work involved an analysis of the structural differences between various manufacturing versions of devices bearing the same type designation, so that the possible effect of the variations on device reliability could be determined. Information contained in this report indicates structural differences between manufacturers devices and indications of sequence of burn-in effects on the generation of failures. The evaluation reveals no serious device problems on initial stress tests and the failures which did occur revealed only anticipated mechanisms at this point in the testing schedule.
APPROVED FOR PUBLIC RELEASE