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Digital Processing Receiver.
Final technical rept.,
GENERAL DYNAMICS SAN DIEGO CALIF ELECTRONICS DIV
Pagination or Media Count:
The study effort investigated cost-effective designs for a single - and multi-channel HF digital processing receiver. The basic design was also applied to an extended frequency range of 30-500 MHz. The conceptual design of the communication receiver has at the heart of the receiver a special purpose, high-speed micro programmed computer that uses emitter coupled logic circuits. The low-speed processing junctions, such as AGC, frequency control, mode of operation, bandwidth and inputoutput, is accomplished by an INTEL 8080 micro processor which also has a limited capability for signal selection. Computer simulations of two multichannel candidate system revealed that both systems could meet all critical performance requirements. Based on hardware considerations, a system using regular bandpass sampling and a recursive processor inplementation was selected as the most cost-effective approach.
APPROVED FOR PUBLIC RELEASE