Accession Number:

ADA008522

Title:

Digital Processing Receiver.

Descriptive Note:

Final technical rept.,

Corporate Author:

GENERAL DYNAMICS SAN DIEGO CALIF ELECTRONICS DIV

Personal Author(s):

• Bjerede,B. E.
• Bartlow,G.
• Bartley,T.
• Clayton,K.
• Fisher,G.

Report Date:

1975-02-01

Pagination or Media Count:

162.0

Abstract:

The study effort investigated cost-effective designs for a single - and multi-channel HF digital processing receiver. The basic design was also applied to an extended frequency range of 30-500 MHz. The conceptual design of the communication receiver has at the heart of the receiver a special purpose, high-speed micro programmed computer that uses emitter coupled logic circuits. The low-speed processing junctions, such as AGC, frequency control, mode of operation, bandwidth and inputoutput, is accomplished by an INTEL 8080 micro processor which also has a limited capability for signal selection. Computer simulations of two multichannel candidate system revealed that both systems could meet all critical performance requirements. Based on hardware considerations, a system using regular bandpass sampling and a recursive processor inplementation was selected as the most cost-effective approach.

Descriptors:

• *RADIO RECEIVERS
• SIGNAL PROCESSING
• DIGITAL SYSTEMS
• HIGH FREQUENCY
• COST EFFECTIVENESS
• PROCESSING
• MULTICHANNEL
• MULTICHANNEL COMMUNICATIONS

Subject Categories:

• Radio Communications

Distribution Statement:

APPROVED FOR PUBLIC RELEASE