Fault Detection through Parallel Processing in Boolean Algebra.
Computer systems modeling and analysis group series rept.,
CALIFORNIA UNIV LOS ANGELES DEPT OF COMPUTER SCIENCE
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This presentation is an overview of the research in progress on fault detection methods for circuits, both combinational circuits and sequential circuits. A summary of some of the existing techniques for minimal test set generation is followed by an introduction to the concept and theory of a minimal test sequence as a new approach for fault detection in combinational circuits. A detailed explanation of Triadic Graph Theory is followed by a summary of the existing techniques for parallel processing in Boolean Algebra. The main contribution of this paper is the extension of the applications of the Boolean Analyzer to the generation of 1 Boolean Differences 2 stuck-at fault tests for a circuit similar to those generated by Roths D-Algorithm and 3 the Test Sequences of a circuit.
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