Accession Number:



Fabrication of Efficient Reconfigurable Neuromorphic Systems

Descriptive Note:

[Technical Report, Final Report]

Corporate Author:

The Research Foundation for State University of New York on behalf of SUNY Polytechnic Institute Col

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The goal of this effort was to fabricate hybrid CMOSRRAM chips that could be used for a variety of Air Force specific applications, using a low-power, reconfigurable framework. Working with collaborators at UT-Knoxville and a number of other institutions, the SUNY Poly team was able to compile a design containing an unique neuromorphic, reconfigurable test chip UT-Knoxville design, a variety of hybrid CMOSRRAM demonstration circuits from UT-Austin, ASU, and a neuromorphic computing demonstrator chip from UT-San Antonio. In addition, the SUNY Poly team designed multiple memory arrays for demonstration of compute in memory operations and analog information encoding. To this end, the SUNY Poly team also developed optimized RRAM testing parameters to 1 maintain high device yield and endurance, 2 enable a large device memory window, and 3 perform analog information encoding using sub-nanosecond pulses. Together, this work provides a framework for ongoing testing and evaluation of hybrid CMOSRRAM circuits by the SUNY Poly team and collaborators. Full testing of the circuits and chips fabricated under this effort is underway at the partnering institutions and will continue under the OUSD NeuroPipe ARAP program.

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[A, Approved For Public Release]