Accession Number:

AD1175768

Title:

Implementation and Characterization of AHR on a Xilinx FPGA

Descriptive Note:

[Technical Report, Master's Thesis]

Corporate Author:

AIR FORCE INSTITUTE OF TECHNOLOGY WRIGHT-PATTERSON AFB OH

Personal Author(s):

• Dittrich, Andrew J

Report Date:

2022-03-24

Pagination or Media Count:

227

Abstract:

The Adaptive-Hybrid Redundancy AHR architecture was modified and tested in hardware using Commercial-Off-The-Shelf COTS Field-Programmable Gate Arrays FPGAs. The AHR architecture mitigates the effects that the Single Event Upset SEU and Single Event Transient SET radiation effects have on processors and was tested on a Microprocessor without Interlocked Pipeline Stages MIPS architecture. The AHR MIPS architecture was implemented on two Xilinx FPGAs using a serial based communication network. The runtime performance of AHR MIPS was measured and compared against the performance of TMR and TSR MIPS. AHR MIPS demonstrated flexible runtime performance that was nearly as fast as TMR MIPS, never as slow as TSR MIPS, and demonstrated performance in between those extremes. Hardware testing and verification of AHR MIPS showed that the AHR mitigation strategy presents a large performance trade space, where a user can adjust both the runtime processor performance and radiation tolerance to fit the constraints of a space mission.

Descriptors:

• instruction set architecture
• air force
• test methods
• energy consumption
• field programmable gate arrays
• test and evaluation
• application-specific integrated circuits
• engineering
• integrated circuits
• radiation effects
• semiconductors
• cell physiological processes
• diagrams
• electrical engineering
• electronics
• radiation
• simulations

Subject Categories:

• Electrical and Electronic Equipment

Distribution Statement:

[A, Approved For Public Release]