Accession Number:

AD1147429

Title:

Logical Analysis of Multiple Clock Domains

Descriptive Note:

[Technical Report, Memorandum Report]

Corporate Author:

NAVAL RESEARCH LAB WASHINGTON DC

Personal Author(s):

Report Date:

2021-08-26

Pagination or Media Count:

30

Abstract:

This is a report on how to manage multiple clock domains from a logical perspective starting from some basic hardware. The hardware isa chain of flip-flops used to synchronize signals from one clock domain to another. The analyses is done in Channel Theory and DistributedLogic. Channel Theory was the precursor to Distributed Logic and both are viable for the analyses. The logical analyses takes the form of apertinent example showing how to represent the key facts necessary for the logic. At the end, the synchronizing primitives of the languagesEsterel, Lustre, and Signal are briefly explained. These languages are early attempts at defining computation by corralling asynchrony to besynchrony. None of the languages has been applied to the authors knowledge to FPGA applications. Yet, the synchrony primitives capture theessential features used in the chain of flip-flops that are used in FPGA applications. Many FPGA applications use message queues to enforce synchronous behavior, the analyses here could have used those. However, the flip-flop use is more basic and presents the key features adequately yet has minimal footprint in hardware.

Descriptors:

Subject Categories:

Distribution Statement:

[A, Approved For Public Release]