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Valleytronic Logic Gate: FY19 Advanced Devices Line-Supported Program

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Technical Report

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MIT Lincoln Laboratory Lexington United States

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Classical computing faces a significant challenge. Field effect transistor technology is reaching the fundamental limits of scaling and no proposed replacement technology has yet demonstrated even comparable performance. A transformational device based on new physical phenomena could provide a new route to continued improvement in microelectronic power and performance. Two-dimensional transition metal dichalcogenides TMDs possess a number of intriguing electronic, photonic, and excitonic properties. This proposal focuses on their Valleytronic properties, which are truly unique to this new class of materials. Due to a lack of inversion symmetry and strong spin-orbit coupling, 2D TMDs possess individually addressable valleys in momentum space at the K and K points in the first Brillouin zone. This valley addressability opens the possibility of using electron and hole momentum states as a completely new paradigm in information processing. Manipulating the K and K momentum states could permit classical computation at a small fraction of the energy cost incurred by traditional field effect transistors. The Valleytronic Logic Gate Line program began to explore the viability of creating a classical logic gate which would provide a PPA power, performance, area advantage over silicon CMOS. It was not within the scope of funding to build a logic gate and test it experimentally. Instead, some basic valleytronic material parameters were measured and using that information an analysis was performed of the power and speed of a notional gate design. Section 1 provides an introduction to valleytronic principles, Section 2 describes the measurements, Section 3 describes the performance projections, Section 4 summarizes the results of the project and Section 5 lists references and Lincoln and MIT external presentations from this work in FY19.

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  • Electrical and Electronic Equipment

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