DE10 Pins and Connections For Basic MIPS
Technical Report,10 Sep 2016,30 Sep 2019
Air Force Institute of Technology Wright-Patterson AFB United States
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This report describes in detail the pins and connections for the Basic MIPS architecture on a Terrasic DE10-Standard board utilizing an Intel Cyclone V FPGA. Specifically, the detailed connections between one DE10-Standard running Basic MIPS, Temporal Software Redundancy TSR MIPS, Triple Modular Redundancy TMR MIPS, or Adaptive-Hybrid Redundancy AHR MIPS and a second DE10-Standard storing a program in a memory emulator are fully documented.
- Computer Hardware
- Electrical and Electronic Equipment