Accession Number:

AD1083728

Title:

DE10 Pins and Connections For Basic MIPS

Descriptive Note:

Technical Report,10 Sep 2016,30 Sep 2019

Corporate Author:

Air Force Institute of Technology Wright-Patterson AFB United States

Personal Author(s):

Report Date:

2019-09-12

Pagination or Media Count:

30.0

Abstract:

This report describes in detail the pins and connections for the Basic MIPS architecture on a Terrasic DE10-Standard board utilizing an Intel Cyclone V FPGA. Specifically, the detailed connections between one DE10-Standard running Basic MIPS, Temporal Software Redundancy TSR MIPS, Triple Modular Redundancy TMR MIPS, or Adaptive-Hybrid Redundancy AHR MIPS and a second DE10-Standard storing a program in a memory emulator are fully documented.

Subject Categories:

  • Computer Hardware
  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE