Accession Number:

AD1083727

Title:

Adaptive-Hybrid Redundancy MIPS Version 2.2

Descriptive Note:

Technical Report,12 Sep 2016,12 Sep 2019

Corporate Author:

Air Force Institute of Technology Wright-Patterson AFB United States

Personal Author(s):

Report Date:

2019-09-12

Pagination or Media Count:

119.0

Abstract:

This report describes in detail the architecture of an Adaptive-Hybrid Redundancy AHR MIPS processor based upon the Basic MIPS processor and Triple Modular Redundancy TMR processor. The AHR MIPS processor is the result of Adaptive-Hybrid Redundancy for Radiation-Hardening research and combines TMR and Temporal Software Redundancy. The AHR MIPS processor is hybrid in that it utilizes both hardware and software redundancy. It is adaptive because it has the capability to switch between TMR and TSR modes. There may be many other applications for the AHR MIPS processor beyond this specific research area.

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE