Accession Number:

AD1083723

Title:

Triple Modular Redundancy MIPS Architecture Version 1.4

Descriptive Note:

Technical Report,12 Sep 2016,12 Sep 2019

Corporate Author:

Air Force Institute of Technology Wright-Patterson AFB United States

Personal Author(s):

Report Date:

2019-09-12

Pagination or Media Count:

114.0

Abstract:

This report describes in detail the architecture of a Triple Modular Redundancy TMR MIPS processor based upon the Basic MIPS processor. The TMR MIPS processor is used for Adaptive-Hybrid Redundancy research. There may be many other applications for the TMR MIPS processor beyond this specific research area.

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE