Triple Modular Redundancy MIPS Architecture Version 1.4
Technical Report,12 Sep 2016,12 Sep 2019
Air Force Institute of Technology Wright-Patterson AFB United States
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This report describes in detail the architecture of a Triple Modular Redundancy TMR MIPS processor based upon the Basic MIPS processor. The TMR MIPS processor is used for Adaptive-Hybrid Redundancy research. There may be many other applications for the TMR MIPS processor beyond this specific research area.
- Computer Hardware