Digital Logic Gate Characterization with Gallium Nitride Transistor
[Technical Report, Master's Thesis]
The Ohio State University
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This thesis presents work on the development of digital logic gates using Gallium Nitride GaN transistors in a 0.25 m process. The allowed minimum width of 12 m is reduced to 5 m in order to observe scalability and to measure the performance benets of smaller device sizes in the GaN process. Due to poor modeling, the designed Buffered FET Logic INV, NOR2, and NAND2 are designed for functionality over performance, resulting from the risk of failure without proper simulations. A preliminary test plan was developed and executed to prove the functionality of the devices across varying temperatures, voltages, and input frequencies, with initial tests indicating that the devices are fully functional across these parameters.
- Computer Hardware