Transient Simulation of High-Voltage Silicon Carbide Super-Gate Turn-off Thyristors (SGTOs) under Extreme Narrow Pulsed Conditions
Technical Report,01 Dec 2018,30 Jun 2019
CCDC Army Research Laboratory Adelphi United States
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This report discusses the failure mechanism of 15-kV silicon carbide super-gate turn-off thyristors SGTOs during extreme high current density 3.85 kAcm2 pulsed operation. It is believed that the failure mechanism of the devices evaluated is attributed to recombination-induced stacking fault SF formation due to the insufficient buffer layer thickness. The SF failure mechanism is supported experimentally by forward voltage degradation observed during long-term pulse evaluation of the SGTO devices during high-current narrow pulse evaluation performed at 0.5 Hz. The report implements technology computer-aided design simulation at the experimental narrow pulse evaluation previously stated. The results reveal a significant level of approx.1014 cm3 minority carrier injection in the buffer layer that penetrates into the substrate region of the device, which could potentially affect the long-term reliability and pulse performance. A model of a high-power SGTO was developed in the Silvaco Atlas software to better understand the extreme electrical stresses in the SGTO when subjected to a high-current pulse. Simulation of the on-state current and device forward voltage drop closely matches measured data. Current density distribution through the device was analyzed, and areas of high minority carrier injection at elevated high current operation were identified.
- Electromagnetic Pulses