Technology-Independent Silicon Camouflage using Virtual Camouflage Front-End Cells
Inside Secure Westminster United States
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Silicon camouflage, a highly effective obfuscation technique to protect hardware IP from reverse engineering and analysis, is typically implemented in a technology-specific camouflaged cell library and inserted into an ICs gate-level netlist. A new camouflaged IC design flow using virtual camouflage cells enables the detailed specification of silicon camouflage features in a designs technology-independent register transfer level RTL models. Using virtual camouflage cells, RTL designers can specify how their hardware IP will utilize camouflaged circuitry while maintaining the models technology independence. This paper introduces the concept of virtual camouflage cells and describes a camouflaged IC design flow that enables camouflage features to be designed in RTL, including the methods by which the technology-independent camouflaged RTL is synthesized to technology-specific cell libraries and implemented at a given technology node.
- Electrical and Electronic Equipment