Quantifying Security and Overheads for Obfuscation of Integrated Circuits
University of Southern California Los Angeles United States
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Logic obfuscation techniques are used to deter intellectual property piracy, reverse engineering, and counterfeiting threats in the manufacturing of integrated circuits IC. The security of these obfuscation algorithms has been, however, compromised by Boolean satisfiability SAT based attacks. SAT attacks can reveal the deobfuscation key in seconds, rendering the IC design vulnerable to reverse engineering. The ever-changing landscape of attacks and defenses are typically vetted on small benchmark circuits where security is measured in terms of the time required to recover the encryption key from the obfuscated circuit. This paper introduces a uniform security metric for evaluating the existing obfuscation methods. The benchmark circuits are synthesized after each obfuscation method to determine the overhead in terms of area, power, and timing, including the impact of logic obfuscation algorithms on practical circuits with reasonable gate count 100K gates. A thorough evaluation is conducted to determine the contributing factors toward attack resiliency time such as gate count, logic depth, and area, power, timing overhead before recommending the best obfuscation method for a specific circuit.