Accession Number:

AD1066447

Title:

Agile 3D Memory Interfaces

Descriptive Note:

Technical Report,01 Aug 2015,31 Aug 2018

Corporate Author:

North Carolina State University Raleigh United States

Report Date:

2019-01-01

Pagination or Media Count:

27.0

Abstract:

The DiRAM4 memory permits fast random access of DRAM via 64 bidirectional memory ports. A memory controller was designed and verified that is suited for interfacing a multicore CPU to this unique DRAM.

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE