Accession Number:

AD1052641

Title:

Pre RTL Voltage and Power Optimization for Low-cost,Thermally Challenged Multicore Chips

Descriptive Note:

Conference Paper

Corporate Author:

University of Virginia Charlottesville United States

Report Date:

2018-03-12

Pagination or Media Count:

4.0

Abstract:

The imminent end of Moores Law demands increasing complexity to enable continuing improvement in the cost and performance of electronic systems. Complex RTL designs lead to long simulation overheads, making it infeasible to explore large design spaces. In this work, we present a flow of simulation tools for rapid, high-level, pre-RTL exploration to enable design-space exploration for physically-constrained systems. This flow updates several prior tools and introduces new tools to support optimization across multiple metrics gem5, a widely-used microarchitecture and memory hierarchy simulator, for performance McPAT, a generalized, ISA-agnostic power and area modeling tool HotSpot, a temperature simulator VoltSpot, a voltage droop simulator and OldSpot, a planned lifetime and reliability simulator. By simulating a workload in gem5 and feeding its results into McPAT and then HotSpot, VoltSpot, and OldSpot, it is possible to explore the effects of workloads on systems with physical constraints such as power or thermal budgets and lifetime targets without requiring complex RTL design or long RTL simulation.

Subject Categories:

  • Electrical and Electronic Equipment
  • Manufacturing and Industrial Engineering and Control of Production Systems

Distribution Statement:

APPROVED FOR PUBLIC RELEASE