Automated SoC Security from Design to Fabrication
University of Florida Gainesville United States
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System-on-chips SoCs are increasingly used in high assurance electronic systems such as military, space, automotive, financial and health care systems. We rely on the security of these SoCs, yet it has been demonstrated that SoCs can be compromised using physical and remote attacks such as timing and power analysis or fault-injection exploits. Manually analyzing circuit implementations for security vulnerabilities is becoming less and less feasible due to the increasing complexity of SoC designs and the integration of multiple third-party IP 3PIP blocks. Security policies also lack formal definitions and rely on ad-hoc solutions at design time. Currently, there exists no systematic, automated solution to deal with SoC vulnerabilities before deployment. To address this, we propose the unified security definition format USDF language for the formal representation of IC security policies and attributes. We extend the design security rule check DSeRC framework and introduce the automated security policy enforcement ASPEN framework. USDF provides a language syntax to formally write security policies and attributes that can be interpreted by the ASPEN framework for automated SoC security analysis.
- Electrical and Electronic Equipment