Accession Number:

AD1050743

Title:

A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers

Descriptive Note:

Technical Report,13 Jun 2016,13 Dec 2017

Corporate Author:

University of California Los Angeles Los Angeles United States

Personal Author(s):

Report Date:

2018-04-01

Pagination or Media Count:

51.0

Abstract:

This report summarizes a year-long study on the applicability of the charge trap transistor CTT for embedded memory applications. Two case uses are considered 1 as a digital multi-time programmable memory and 2 as are programmable analog memory. Experimental data reveals that a CTT for analog memory applications possesses promising characteristics for implementing synapses in neural networks, such as spike-timing dependent plasticity, very fine tunability, weight-dependent plasticity, and low power consumption. Ongoing efforts include the design and tape out of a CTT-based neuromorphic chip for digit recognition, and more elaborate designs that address programming time, scalability, powerarea reduction, redundancy, unsupervised learning, etc. in the long-term.

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE