A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers
Technical Report,13 Jun 2016,13 Dec 2017
University of California Los Angeles Los Angeles United States
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This report summarizes a year-long study on the applicability of the charge trap transistor CTT for embedded memory applications. Two case uses are considered 1 as a digital multi-time programmable memory and 2 as are programmable analog memory. Experimental data reveals that a CTT for analog memory applications possesses promising characteristics for implementing synapses in neural networks, such as spike-timing dependent plasticity, very fine tunability, weight-dependent plasticity, and low power consumption. Ongoing efforts include the design and tape out of a CTT-based neuromorphic chip for digit recognition, and more elaborate designs that address programming time, scalability, powerarea reduction, redundancy, unsupervised learning, etc. in the long-term.
- Electrical and Electronic Equipment