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CLEAR: Cross-Layer Exploration for Architecting Resilience

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Conference Paper

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Stanford University Stanford United States

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CLEAR is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures achieve desired resilience targets at minimal costsenergy, power, execution time, area by combining resilience techniques across various layers of the system stack circuit, logic, architecture, software, algorithm. CLEAR automatically and systematically explores the large space of techniques and their combinations 586 cross-layer combinations in this paper, derives cost-effective solutions, and provides guidelines for designing new techniques. Carefully optimized combinations of circuit-level hardening, logic-level parity checking, and micro-architectural recovery provide highly cost-effective soft error resilience for general-purpose processor cores. 50x silent data corruption rate improvement is achieved at 2.1 energy cost for out-of-order 6.1 for in-order cores, with no speed impact. Selective circuit-level hardening alone, guided by thorough application benchmark analysis, also provides cost-effective solutions 1 additional energy cost for the same 50x improvement.

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  • Computer Hardware

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