Side Channel Attacks on STTRAM and Low Overhead Countermeasures
Pennsylvania State University University Park United States
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Spin-Torque Transfer RAM STTRAM, although promising, suffers from high write latency and write current. Additionally, the latency and current depends on the polarity of the data being written. These factors introduce security vulnerabilities and expose the cache memory to side channel attacks. In this paper, we propose a side channel attack SCA model where the adversary can monitor the supply current of the memory array to partially identify the sensitive cache data that is being read or written. We propose solutions such as short retention STTRAM, obfuscation of SCA using 1-bit parity, multi-bit random write, and, neutralizing the SCA using constant current write driver to mitigate such attacks.
- Electrical and Electronic Equipment