Building a Library for Microelectronics Verification with Topological Constraints
513th Electronic Warfare Squadron Eglin AFB United States
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This paper proposes a methodology to build a library for gate-level microelectronics verification with topological constraints. Circuits at the second level of abstraction are selected from prior work on simulated reverse-engineered hardware. We show that when signal pairs are switched while maintaining circuit functionality, the topological genus varies according to a frequency distribution that differs for each circuit.
- Electrical and Electronic Equipment