Accession Number:

AD1041375

Title:

Building a Library for Microelectronics Verification with Topological Constraints

Descriptive Note:

Conference Paper

Corporate Author:

513th Electronic Warfare Squadron Eglin AFB United States

Personal Author(s):

• Hsia,Leleia A
• Vernizzi,Graziano
• Lanzerotti,Mary Y
• Langley,Derrick

Report Date:

2017-03-01

Pagination or Media Count:

4.0

Abstract:

This paper proposes a methodology to build a library for gate-level microelectronics verification with topological constraints. Circuits at the second level of abstraction are selected from prior work on simulated reverse-engineered hardware. We show that when signal pairs are switched while maintaining circuit functionality, the topological genus varies according to a frequency distribution that differs for each circuit.

Descriptors:

• xor gates
• permutations
• equivalent circuits
• electrical properties
• topology
• circuit analysis
• Microelectronics
• validation

Subject Categories:

• Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE