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PDSparc: A Drop-in Replacement for LEON3 Written Using Synopsys Processor Designer

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Technical Report

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MIT Lincoln Laboratory Lexington United States

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Microprocessors are the engines that drive the modern world. For decades this space has been dominated by large manufacturers, such as Intel and AMD, which design and fabricate a range of stand-alone processors. However the proliferation of small computing devices such as cellular phones, laptop computers, and internet-enabled appliances has opened a significant new niche the Application Specific Standard Product ASSP microprocessor. These processors typically start out as soft-cores that are parameterized at design time to realize exclusively the specific needs of the application. The microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its function. Therefore, creating a full system requires significant top-level integration.This work introduces PDSparc, an ASSP based on the OpenSparc architecture. PDSparc was generated using the Synopsys Processor Designer PD tool, which enables detailed specification of a pipelined processor using a C-like language called LISA 13. PDSparc replaces a LEON3 processor, a derivative of the Sparc v8 microarchitecture 5, in a full synthesizable SoC system 3 provided by Cobham Gaisler under the Gnu Public License. This integration required significant reverse engineering of the provided cache interfaces and was facilitated by a novel socket-based debug interface to the PDSparc simulation model. This debug interface greatly accelerated system development by permitting micro-stepping of the PDSparc processor code in synchronization with the peripherals and bus package running on a commercial RTL simulator. We anticipate that this paper will be of interest to the practitioners in the field who can use the approach and the lessons learned in building their own processor execution cores.

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  • Computer Hardware

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