Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits
Journal Article - Open Access
MIT Lincoln Laboratory Lexington United States
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We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum SFQ digital circuits with very large-scale integration on 200-mm wafers the SFQ4ee and SFQ5ee nodes, where ee denotes that the process is tuned for energy-efficient SFQ circuits. The former has eight superconducting layers with 0.5-m minimum feature size and a 2-sq Mo layer for circuit resistors. The latter has nine superconducting layers eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoN x layer T c 7.5 K with high kinetic inductance about 8 pHsq for forming compact inductors. A nonsuperconducting T c 2 K MoN x layer with lower nitrogen content is used for 6-sq planar resistors for shunting and biasing of Josephson junctions JJs. Another resistive layer is added to form interlayer sandwich-type resistors of milliohm range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use AuPtTi contact metallization for chip packaging. The technology utilizes one layer of NbAlO x -AlNb JJs with critical current density J c of 100 Am 2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high-density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization of SiO 2 interlayer dielectric. The following results and topics are presented and discussed the effect of surface topography under the JJs on the their properties and repeatability, I c and J c targeting, effect of hydrogen dissolved in Nb, MoN x properties for the resistor layer and for high-kinetic-inductance layer, and technology of milliohm-range resistors.
- Electrical and Electronic Equipment