In-Storage Embedded Accelerator for Sparse Pattern Processing
MIT Lincoln Laboratory Lexington United States
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We present a novel system architecture for sparse pattern processing, using flash storage and an in-storage embedded accelerator. Placing commonly used computing kernels in direct access to a data source achieves high performance, without increasing the requirements for system memory. We show that the sparse pattern matching accelerator is useful for general sparse vector multiplication, feature matching, subgraph matching, protein database search, and machine learning applications. In our prototyping experiment, one accelerator slice can outperform a 16-core system at a fraction of the power and cost.
- Computer Hardware