Heterogeneous IP Ecosystem enabling Reuse (HIER)
Technical Report,01 Jan 2016,31 Dec 2016
UNIVERSITY OF SOUTHERN CALIFORNIA LOS ANGELES LOS ANGELES United States
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In the Department of Defense DoD world, an Intellectual Property IP re-use infrastructure has been lacking, even in the digital domain. Significant investments in custom chip designs have been made by the government, but the IP resulting from such efforts is not readily available for re-use, and even in cases where IP is available, porting to a common implementation platform for integration is often cost-prohibitive. Thus, an execution model and infrastructure to enable DoD-specific IP reuse is greatly needed. While such an effort is more of an infrastructure development rather than a research endeavor, it would pay handsome dividends to the DoD with respect to more efficient, lower cost chip design efforts in the future. IP re-use for heterogeneous integration is even more challenging. IP from widely disparate technologies including silicon CMOSBiCMOS, compound semiconductors including InPGaNGaAsInGaAs need to be properly modeled and simulated in an integrated environment. The University of Southern California conducted an exploratory effort to formulate the detailed requirements for accomplishing a successful Heterogeneous IP Ecosystem enabling Reuse HIER. The HIER project explored both fabrication process issues as well as tools issues. The results of the study identified where major investment is needed to make such a paradigm be as seamless as possible. In the course of the HIER project, DARPA also established additional concepts in the formation of the Common Heterogeneous Integration and IP Reuse Strategies CHIPS program. In response to the request for information and broad agency announcement associated with the CHIPS program, the HIER project refined its approach to address requirements for that program.
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