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Read-In Integrated Circuits for Large-Format Multi-Chip Emitter Arrays

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Conference Paper

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University of Delaware Newark United States

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Conventional read-in integrated circuit RIIC designs use a layout approach where a single emitter pixel is duplicated and formed into an array. On the periphery of the emitter pixel array are the addressing circuits and wire bond pads are placed. This layout approach cannot be used for multi-chip RIIC arrays with Through Substrate Vias TSVs because there is no room for decoder and IO circuits on the periphery of the chip. Also the diameter of the TSV is much larger than the pixel pitch e.g. TSV diameter is typically 100-microns while emitter pixel pitch is 48-microns. Our paper describes a novel RIIC design to overcome this using a novel layout approach that distributes address decoding circuits and TSVs throughout the driver array. The paper also discusses a novel abuttment method for creating multi-chip arrays. A prototype RIIC chip has been designed and fabricated using ONSEMI C5N process to verify our approach.

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  • Electrical and Electronic Equipment

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