The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
Massachusetts Institute of Technology Cambridge United States
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The Raw microprocessor consumes 122 million transistors executes 16 different load, store, integer, or floating-point instructions every cycle controls 25 Gbytess of inputoutput IO bandwidth and has 2 Mbytes of on-chip distributed L1 static RAM providing on-chip memory bandwidth of 57 Gbytess. Is this the latest billion-dollar, 3,000 man-year processor effort In fact, it took only a handful of graduate students at the Laboratory for Computer Science at MIT to design and implement Raw. Our research addresses a key technological problem for microprocessor architects How to leverage growing quantities of chip resources even as wire delays become substantial. The Raw research prototype uses a scalable instruction set architecture ISA to attack the emerging wire-delay problem by providing aparallel, software interface to the gate, wire, and pin resources of the chip. An architecture that has direct, first-class analogs to all of these physical resources will ultimately let programmers achieve the maximum amount of performance and energy efficiency in the face of wire delay. Existing architectural abstractions, such as interrupts, caches, context switches, and virtualization can continue to be supported in this environment, even as a new low-latency communication mechanismthe static networkenables new application domains.
- Computer Hardware
- Computer Programming and Software