Accession Number:

AD1002544

Title:

Demonstration of Inexact Computing Implemented in the JPEG Compression Algorithm using Probabilistic Boolean Logic applied to CMOS Components

Descriptive Note:

Technical Report,01 Sep 2012,24 Dec 2015

Corporate Author:

Air Force Institute of Technology WPAFB United States

Personal Author(s):

• Allen,Christopher I

Report Date:

2015-12-24

Pagination or Media Count:

283.0

Abstract:

Probabilistic computing offers potential improvements in energy, performance, and area compared with traditional digital design. This dissertation quantifies energy and energy-delay tradeoffs in digital adders, multipliers, and the JPEG image compression algorithm. This research shows that energy demand can be cut in half with noisesusceptible16-bit Kogge-Stone adders that deviate from the correct value by an average of 3 in 14 nanometer CMOS FinFET technology, while the energy-delay product EDP is reduced by 38 . This is achieved by reducing the power supply voltage which drives the noisy transistors. If a 19 average error is allowed, the adders are 13 times more energy-efficient and the EDP is reduced by 35 . This research demonstrates that 92 of the color space transform and discrete cosine transform circuits within the JPEG algorithm can be built from inexact components, and still produce readable images. Given the case in which each binary logic gate has a 1 error probability, the color space transformation has an average pixel error of 5.4 and a 55 energy reduction compared to the error-free circuit, and the discrete cosine transformation has a 55 energy reduction with an average pixel error of 20 .

Descriptors:

• probability distributions
• power supplies
• logic gates
• energy consumption
• integrated circuits
• BOOLEAN FUNCTIONS
• image compression

Subject Categories:

Distribution Statement:

APPROVED FOR PUBLIC RELEASE