Accession Number:

AD0912518

Title:

High Speed Parallel to Serial to Parallel Multiplexers.

Descriptive Note:

Final rept. 1 May 72-30 Apr 73,

Corporate Author:

TRW SYSTEMS GROUP REDONDO BEACH CA

Report Date:

1973-08-01

Pagination or Media Count:

77.0

Abstract:

This report describes the design and development of a high speed multiplexerdemultiplexer system with digital circuits capable of operating at subnanosecond switching speeds and at serial data rates through 1 gigabit per second. The equipment developed consists of a high speed 8-to-1 digital multiplexer, a high speed 1-to-8 digital demultiplexer, and an 8-to-48 line data-expander. An eight line pattern generator synchronous binary counter is incorporated within the multiplexer unit alond with a sync code generator and a parity generator. In the normal mode of operation the multiplexer accepts 8-bit words 6 data bits, 1 parity bit, 1 sync bit and multiplexes these up to a single 1Gbs serial data stream. The demultiplexer unit accepts the 1Gbs serial NRZ data and demultiplexes it back to parallel 8-bit groupings. The data expander searches these eight parallel lines for the sync code, regroups the incoming bits back into the original 8-bit words, and expands these words to a sixword synchronous parallel interface. A DA converter is provided within the data expander unit to allow conversion of the binary count sequence input to the multiplexer to a staircase waveform. The system provides considerable flexibility and was specifically designed for variable frequency operation from dc to beyond 1 Gbs. The high speed multiplexing, demultiplexing, and timing for these functions is performed by thin film hybrid logic circuits that exhibit gate speed-power products of 10 picojoules, and latch flip-flop performance of 20 megahertz per milliwatt. Author

Subject Categories:

  • Computer Programming and Software
  • Computer Hardware
  • Non-Radio Communications

Distribution Statement:

APPROVED FOR PUBLIC RELEASE