Reliability Evaluation of LSI Microcircuits.
Final rept. Apr 71-Oct 72,
ROCKWELL INTERNATIONAL ANAHEIM CA AUTONETICS GROUP
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The objectives of this evaluation were to 1 define common failure modes 2 document failure analysis and 3 develop better and lower cost electrical and stress test techniques for predicting, assessing, and assuring the reliability of LSI microcircuits. The approach to the evaluation included a canvass of the industry for failure modes experienced, tests used, and available process and logic function types. Next, an optimized and practical set of electrical tests and electrical-thermal stress tests were formulated for a quantity of 595 devices selected having hermetically sealed packages and manufacturing date in the first quarter of 1971. Process types included PMOS, PMOS ion implant, PMOS silicon gate, PMOS molybdenum gate, CMOS, bipolar, discretionary wired bipolar and Schottky diode clamped bipolar. Logic functions included a decade counter, five shift registers, a digital multiplier, five random access memories, and a time buffer register. Following the stress tests, devices were life tested at 125 C under dynamic excitation, power and load. Failed devices were analyzed at the subcomponent level. Related efforts included in the evaluation are covered in this report, such as failure modes experienced, tests, normal stabilities for device test data, and test effectiveness, for MOS and bipolar LSI microcircuits, and a failure rate prediction for several MOS microcircuits. Author
- Electrical and Electronic Equipment
- Computer Hardware