Final rept. Jun 1970-Mar 1973
BURROUGHS CORP PAOLI PA ADVANCED DEVELOPMENT ORGANIZATION
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The aerospace multiprocessor described is based upon a modular, building block approach. An exchange concept that is expandable with the number of processors, memory modules, and device ports, was developed whose path width is a function of the amount of serialization desired in the transmission of data and address through the exchange. The processors called Interpreters are microprogrammable utilizing a 2-level microprogram memory structure and were designed for implementation with large scale integrated circuits. The modularity exhibited in the Interpreters is in the size of the microprogram memories and in the word length of the Interpreters from 8 bits through 64 bits in 8-bit increments. The specific implementation of the exchange for the aerospace multiprocessor is for five processors, eight memory modules, and eight device ports with eight wires each carrying four serial bits of data through the exchange. The processors each have word lengths of 32 bits with a 512 word x 15 bits first-level microprogram memory and a 256 word x 54 bit second-level microprogram memory. A simplified control program based upon concepts for a modular executive structure, and some user type programs were written for demonstration of the aerospace multiprocessor.
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