E-Beam Signal Processor Design
Final technical rept.
NORTHROP RESEARCH AND TECHNOLOGY CENTERPALOS VERDES PENINSULA CA
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The significance of this research and development to the Air Force is that a dual stage signal processor system has been developed which has a potential capability of achieving output data rates exceeding 2 Gbitsec. The design is realized by a state-of-the-art solid state stage and an Electron-Beam- Semiconductor signal processor assembled in series. The former is fabricated from commercially available IC logic chips and has been efficiently interfaced with the EBS processor. The solid state processor multiplexes 64 ns input data pulses into 8 ns pulses to drive the EBS signal processor. The latter multiplexes 8 ns data pulses from 16 input lines into a single output. In this approach, information is placed on the electron beam and read out at the semiconductor target. Output pulse amplitude of one volt into 50 ohm and a pulse width of 0.5 ns has been achieved.
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