Radiation Screening Techniques for Integrated Circuits.
Technical rept. Jan 69-Mar 70,
LOCKHEED MISSILES AND SPACE CO INC SUNNYVALE CA
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Three new approaches are presented for use as neutron screening of the ICs in a manufacturing or assembly environment. For selected types of digital ICs, a technique called Multiple Rise Time is introduced and demonstrated. The technique makes use of several rise time measurements to solve for h sub FE and f sub T of the critical transistors. The operational amplifier open loop gain is treated like h sub FE in an adaptation of the Messenger-Spratt equation to obtain a Wafer Peculiar Damage Constant by a neutron exposure of one IC from each wafer. The Wafer Peculiar Damage Constant is, in turn, applied to the balance of the ICs from the wafer. A new universal approach, called Wafer Annealing, which is possible applicable to all ICs regardless of the construction technology employed, is discussed and demonstrated. While the ICs are still in the wafer stage of the fabrication process, they are exposed to the proper level of neutron fluence, probed, and the defective ones inked. The wafer of ICs is annealed back to its original condition e.g., open loop gain of the operational amplifiers returned to within 95 percent of their original values after 10 to the 15th power nsq cm at an elevated temperature in a suitable atmosphere and returned to the normal processing steps. It is not expected that the irradiate-anneal steps will introduce any measurable change in the reliability. Author
- Electrical and Electronic Equipment